A liquid crystal monitor has since been put to use as a display of personal computers, rapidly replacing a CRT. With the liquid crystal monitor of today, a VGA connector is in use for an interface, however, in the case of a system connected via the VGA connector, processing inside equipment is executed with digital signals, and transmission is executed with analog signals. Since video signals are high frequency signals, the signals are distorted in an analog transmission system, and if the distorted signals are sent out to the liquid crystal monitor as they are, this will result in degradation of display quality of liquid crystals. Accordingly, a DVI (Digital Visual Interface) used for digital transmission has lately become a focus of attention.
FIG. 10 is a block diagram showing a video card 110 connected with a liquid crystal controller 120 via a DVI cable 130. The video card 110 is made up of a video controller 111, a TMDS (Transition Minimized Differential Signaling) transmitter (encoder) 112, and a DVI connector 113 while the liquid crystal controller 120 is made up of a DVI connector 121, a TMDS receiver (decoder) 122, and a panel interface 123. TMDS is a digital transmission system of video signals for noise reduction and DC balance, specifying a transmission system of video signals (use is made of 3 pairs (R, G, B) of data signals and 1 pair of system clock signals) between an output circuit of video signals on the video card and an input circuit thereof on the side of a display. With the use of the DVI connectors, digital signals are transmitted and processed from an input to the liquid crystal controller, shown in FIG. 10.
When sampling a stream of serial data entered into a display device via the DVI, there occurs a problem of clock skew. The clock skew occurs in the case where the phase of a clock signal, for use in determining a time of sampling serial data, deviates from the phase of a serial data signal. The clock skew tends to occur in the case where, for example, a cable for transmission of the clock signal differs in respect of quality, cable length, and density from a cable for transmission of the serial data signal.
Techniques for resolving the problem of the clock skew are disclosed in, for example, JP-B- 3112688. In the case of the techniques, synchronization and discrimination of data are implemented by majority determination of serial data three-times over-sampled, however, a serial data recovery system of the invention according to JP-B- 3112688, comprises a PLL, a multi-bit block assembly, an inter-channel synchronous circuit, and so forth, and is therefore complex in circuit configuration, so that a circuit simple in configuration has been highly desired. Further, since unstable data affected by a jitter component is used as a basis of determination by majority, there is a problem with certainty as for results of determination on “0s”, “1s”, so that a jitter problem caused by variation of a clock itself could not be resolved by the techniques described above.
It is assumed that the DVI is long in cable length in a range of 3 to 10 m, and the longer a cable is, the more susceptible to the effect of performance on a transmitter side the DVI becomes, so that data come to contain jitters and skews.
Such jitters and skews give rise to jitters of images and jitters of a screen when image signals are displayed on a display device, thereby creating a major cause of difficulty to see.